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ksz8041tl/ftl/mll 10base-t/100base-tx/100base-fx physical layer transceiver data sheet rev. 1.2 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com december 2009 m9999-120909-1.2 general description the ksz8041tl is a single supply 10base-t/100base-tx physical layer transceiver, which provides mii/rmii/smii interfaces to transmit and receive data. it utilizes a unique mixed-signal design to extend signaling distance while reducing power consumption. hp auto mdi/mdi-x provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. micrel linkmd ? tdr-based cable diagnostics permit identification of faulty copper cabling. the ksz8041tl represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10bas e-t/100base-tx applications. the ksz8041ftl has all the identical rich features of the ksz8041tl plus 100base-fx support for fiber and media converter applications. the KSZ8041MLL is the basic 10base-t/100base-tx physical layer transceiver version with mii support. the ksz8041tl and ksz8041ftl are available in 48-pin, lead-free tqfp packages. the KSZ8041MLL is provided in the 48-pin, lead-free lqfp package (see ordering information). data sheets and support documentation can be found on micrels web site at: www.micrel.com. functional diagram ksz8041tl/ftl KSZ8041MLL
micrel, inc. ksz8041tl/ftl/mll december 2009 2 m9999-120909-1.2 features single-chip 10base-t/100base-tx physical layer solution fully compliant to ieee 802.3u standard low power cmos design, power consumption of <180mw hp auto mdi/mdi-x for reliable detection and correction for straight-through and crossover cables with disable and enable option robust operation over standard cables linkmd ? tdr-based cable diagnostics for identification of faulty copper cabling fiber support: 100base-fx (ksz8041ftl only), back-to-back mode support for 100mbps repeater or media converter mii interface support rmii interface support with external 50mhz system clock (ksz8041tl/ftl only) smii interface support with external 125mhz system clock and 12.5mhz sync clock from mac (ksz8041tl/ftl only) miim (mdc/mdio) management bus to 12.5mhz for rapid phy register configuration interrupt pin option programmable led outputs for link, activity and speed power down and power saving modes single power supply (3.3v) built-in 1.8v regulator for core available packages: 48-pin lqfp (KSZ8041MLL) 48-pin tqfp (ksz8041tl/ftl) applications printer lom game console iptv ip phone ip set-top box media converter ordering information part number (marking) ordering number temp. range package lead finish description KSZ8041MLL KSZ8041MLL 0c to 70c 48-pin lqfp pb-free mii, 10/100 copper, c-temp, 48-lqfp ksz8041tl ksz8041tl 0c to 70c 48-pin tqfp pb-free mii / rmii, 10/100 copper, c-temp, 48-tqfp ksz8041tli (1) ksz8041tli -40c to 85c 48-pin tqfp pb-free mii / rmii, 10/100 copper, i-temp, 48-tqfp ksz8041ftl ksz8041ftl 0c to 70c 48-pin tqfp pb-fre e mii / rmii, 100base-fx fiber, c-temp, 48-tqfp ksz8041ftli (1) ksz8041ftli -40c to 85c 48-pin tqfp pb-free mii / rmii, 100base-fx fiber, i-temp, 48-tqfp ksz8041tl (1) ksz8041tl-s 0c to 70c 48-pin tqfp pb-free smii, 10/100 copper, c-temp, 48-tqfp ksz8041tli (1) ksz8041tli-s -40c to 85c 48-pin tqfp pb-free smii, 10/100 copper, i-temp, 48-tqfp ksz8041ftl (1) ksz8041ftl-s 0c to 70c 48-pin tqfp pb-free smii, 100base-fx fiber, c-temp, 48-tqfp ksz8041ftli (1) ksz8041ftli-s -40c to 85c 48-pin tqfp pb-free smii, 100base-fx fiber, i-temp, 48-tqfp note: 1. contact factory for lead time.
micrel, inc. ksz8041tl/ftl/mll december 2009 3 m9999-120909-1.2 revision history revision date summary of changes 1.0 12/21/06 data sheet created. 1.1 4/27/07 added maximum mdc clock speed. added 40k +/-30% to note 1 of pin description and strapping options tables for internal pull-ups/pull- downs. changed model number in register 3h C phy identifier 2. changed polarity (swapped definition) of duplex strapping pin. removed duplex strapping pin update to register 4h C auto-negotiation advertisement bits [8, 6]. added back-to-back mode for ksz8041tl. added symbol error to mii/rmii receive error description and register 15h C rxer counter. added a 100pf capacitor on rext (pin 16) in pin description table. 1.2 12/9/09 updated ordering information. changed mdio hold time (min) from 10ns to 4ns. added thermal resistance ( jc ). added chip maximum current consumption. added led drive current. renamed register 3h bits [3:0] to manufacturers revision number and changed default value to indicates silicon revision. updated rmii output delay for crsdv and rxd[1:0] output pins. added support for asymmetric pause in register 4h bit [11]. added control bits for 100base-tx preamble restore (register 14h bit [7]) and 10base-t preamble restore (register 14h bit [6]). changed strapping pin definition for config[2:0] = 100 from pcs loopback to mii 100mbps preamble restore. corrected mii timing for t rlat , t crs1 , t crs2 . added smii timing. added KSZ8041MLL device and updated entire data sheet accordingly. added 48-pin lqfp package information.
micrel, inc. ksz8041tl/ftl/mll december 2009 4 m9999-120909-1.2 contents general description ............................................................................................................ .................................................. 1 functional diagram.............................................................................................................. ................................................. 1 features ....................................................................................................................... .......................................................... 2 applications................................................................................................................... ........................................................ 2 ordering info rmation ........................................................................................................... ................................................. 2 revision hi story............................................................................................................... ..................................................... 3 list of figures................................................................................................................ ........................................................ 6 list of tables ................................................................................................................. ........................................................ 7 pin configuration ? ksz8041tl .................................................................................................. ........................................ 8 pin configuration ? ksz8041ftl ................................................................................................. ....................................... 9 pin description- ksz8041tl/ftl ................................................................................................. ..................................... 10 strapping options- ksz 8041tl/ftl ............................................................................................... .................................. 15 pin configuration ?KSZ8041MLL .................................................................................................. .................................... 17 pin description? KSZ8041MLL .................................................................................................... ...................................... 18 strapping options ? KSZ8041MLL ................................................................................................. ................................... 21 functional descrip tion ......................................................................................................... .............................................. 22 100base-tx transm it............................................................................................................ ........................................... 22 100base-tx receive............................................................................................................. ........................................... 22 pll clock synthesizer.......................................................................................................... ............................................ 22 scrambler/de-scrambler (100base-tx only)....................................................................................... ............................. 22 10base-t trans mit .............................................................................................................. ............................................. 22 10base-t rece ive ............................................................................................................... ............................................. 23 sqe and jabber function (10base-t only)........................................................................................ .............................. 23 auto-negotiatio n ............................................................................................................... ................................................ 23 mii management (miim) interface ................................................................................................ .................................... 25 interrupt (intrp) .............................................................................................................. ................................................ 25 mii data interface ............................................................................................................. ................................................ 25 mii signal de finition.......................................................................................................... ................................................ 26 transmit clock (t xc) ........................................................................................................... ...................................... 26 transmit enable (txen)......................................................................................................... .................................... 26 transmit data [3:0] (txd[3:0])................................................................................................. .................................. 26 receive clock (rxc) ............................................................................................................ ...................................... 26 receive data valid (rxdv) ...................................................................................................... .................................. 27 receive data [3:0] (rxd[3:0]) .................................................................................................. .................................. 27 receive error (rxer)........................................................................................................... ...................................... 27 carrier sense (crs) ............................................................................................................ ....................................... 27 collision (col) ................................................................................................................. .......................................... 27 reduced mii (rmii) data interface (ksz8041tl/ftl only)......................................................................... .................... 27 rmii signal definition (ks z8041tl/ftl only) .................................................................................... ............................. 28 reference clock (ref_clk) ...................................................................................................... ............................... 28 transmit enable (tx_en)........................................................................................................ ................................... 28 transmit data [1:0] (txd[1:0])................................................................................................. .................................. 28 carrier sense/receive data valid (crs_dv) ...................................................................................... ..................... 28 receive data [1:0] (rxd[1:0]) .................................................................................................. .................................. 28 receive error (rx_ er).......................................................................................................... ..................................... 28 collision de tection ............................................................................................................ ......................................... 29 serial mii (smii) data interfac e (ksz8041tl/ftl only) .......................................................................... ........................ 29
micrel, inc. ksz8041tl/ftl/mll december 2009 5 m9999-120909-1.2 smii signal definition (ksz8041t l/ftl only).................................................................................... .............................. 29 clock reference (clock) ........................................................................................................ ................................. 29 sync pulse (sync) .............................................................................................................. ....................................... 29 transmit data and control (tx) ................................................................................................. ............................... 29 receive data a nd control (rx).................................................................................................. ................................ 30 collision de tection ............................................................................................................ ......................................... 31 hp auto mdi/mdi -x.............................................................................................................. ............................................ 32 straight cable ................................................................................................................. ............................................ 32 crossover cable ................................................................................................................. ........................................ 33 linkmd ? cable diag nostics............................................................................................................. ................................. 34 access ......................................................................................................................... ................................................ 34 usage .......................................................................................................................... ................................................. 34 power managem ent............................................................................................................... ........................................... 34 power saving mode.............................................................................................................. ...................................... 34 power down mode................................................................................................................ ...................................... 34 reference clock co nnection options ............................................................................................. ................................. 35 reference circuit for power and ground connections ............................................................................. ....................... 36 100base-fx fiber operation (ksz8041ftl only) ................................................................................... ........................ 37 fiber signal detect ............................................................................................................ ......................................... 37 far-end fault................................................................................................................... ............................................ 37 back-to-back media converter................................................................................................... ...................................... 38 mii back-to-b ack mode .......................................................................................................... .................................... 38 rmii back-to-back mode (ksz8041tl/ftl only) .................................................................................... ................ 39 register map................................................................................................................... ..................................................... 40 register de scription ........................................................................................................... ................................................ 40 absolute maximum ratings (1) ............................................................................................................................... ............. 48 operating ratings (2) ............................................................................................................................... ............................. 48 electrical characteristics (3) ............................................................................................................................... ................. 48 timing diagrams ................................................................................................................ ................................................. 50 mii sqe timing (10bas e-t) ...................................................................................................... ....................................... 50 mii transmit timi ng (10base-t) ................................................................................................. ...................................... 51 mii receive timi ng (10base-t) .................................................................................................. ...................................... 52 mii transmit timing (100base-tx) ............................................................................................... ................................... 53 mii receive timi ng (100bas e-tx) ................................................................................................ ................................... 54 rmii timing.................................................................................................................... ................................................... 55 smii timing.................................................................................................................... ................................................... 56 auto-negotiation timing ........................................................................................................ ........................................... 57 mdc/mdio timing ................................................................................................................ ........................................... 58 reset timing................................................................................................................... .................................................. 59 reset circui t .................................................................................................................. ...................................................... 60 selection of isolation transformer............................................................................................. ....................................... 62 selection of reference crystal ................................................................................................. ......................................... 62 package information............................................................................................................ ............................................... 63 48-pin lqfp .................................................................................................................... ................................................. 63 48-pin tqfp .................................................................................................................... ................................................. 64
micrel, inc. ksz8041tl/ftl/mll december 2009 6 m9999-120909-1.2 list of figures figure 1. auto-negotiation flow chart......................................................................................... ........................................ 24 figure 2. smii trans mit data/control segment.................................................................................. ................................. 30 figure 3. smii recei ve data/control segment................................................................................... ................................. 31 figure 4. typical stra ight cable connection ................................................................................... .................................... 32 figure 5. typical cros sover cable connection .................................................................................. ................................. 33 figure 6. 25mhz crystal / osc illator reference clock for mii mode ............................................................. ...................... 35 figure 7. 50mhz oscillator re ference clock for rmii mode...................................................................... ......................... 35 figure 8. 125mhz oscillator reference clock for smii mode ..................................................................... ........................ 35 figure 9. ksz8041tl/ftl/mll power and ground connections...................................................................... ................. 36 figure 10. ksz8041tl/mll and ksz8041ft l back-to-back media converter.......................................................... ....... 38 figure 11. mii sqe timing (10base-t) .......................................................................................... ..................................... 50 figure 12. mii trans mit timing (10base-t) ..................................................................................... .................................... 51 figure 13. mii recei ve timing (10base-t) ...................................................................................... .................................... 52 figure 14. mii transmi t timing (100base-tx)................................................................................... .................................. 53 figure 15. mii recei ve timing (100base-tx).................................................................................... .................................. 54 figure 16. rmii timing C data received from rmii .............................................................................. .............................. 55 figure 17. rmii timing C data input to rmii ................................................................................... .................................... 55 figure 18. smii timing C data received from smii .............................................................................. .............................. 56 figure 19. smii timing C data input to smii................................................................................... ..................................... 56 figure 20. auto-negotiation fast link pulse (flp) timing ...................................................................... ........................... 57 figure 21. mdc/ mdio timing.................................................................................................... .......................................... 58 figure 22. re set timing....................................................................................................... ................................................ 59 figure 23. recommen ded reset circuit.......................................................................................... .................................... 60 figure 24. recommended reset circuit for interfacing with cpu/ fpga reset output ............................................... ...... 60 figure 25. reference circuits for led strapping pins.......................................................................... ............................... 61
micrel, inc. ksz8041tl/ftl/mll december 2009 7 m9999-120909-1.2 list of tables table 1. mii management frame format .......................................................................................... .................................. 25 table 2. mii signal definition ................................................................................................ ............................................... 26 table 3. rmii signal description.............................................................................................. ............................................ 28 table 4. smii si gnal description.............................................................................................. ............................................ 29 table 5. smii tx bit description .............................................................................................. ............................................ 30 table 6. smii txd[0: 7] encoding table ......................................................................................... ..................................... 30 table 7. smii rx bit description.............................................................................................. ............................................ 31 table 8. smii rxd[0: 7] encoding table ......................................................................................... ..................................... 31 table 9. mdi/mdi-x pin definition ............................................................................................. .......................................... 32 table 10. ksz8041tl/ftl/mll power pin de scription............................................................................. ......................... 36 table 11. copper and fi ber mode selection ..................................................................................... .................................. 37 table 12. mii signal connection for mii back-to-back mode ..................................................................... ......................... 38 table 13. rmii signal connection for rmii back-t o-back mode................................................................... ...................... 39 table 14. mii sqe timing (10base-t) parameters ................................................................................ ............................. 50 table 15. mii transm it timing (10base-t) parameters ........................................................................... ........................... 51 table 16. mii receive timing (10base-t) parameters ............................................................................ ........................... 52 table 17. mii transmit ti ming (100base-tx) parameters ......................................................................... ......................... 53 table 18. mii receive timing (100base-tx) parameters .......................................................................... ......................... 54 table 19. rmii timing parameters .............................................................................................. ........................................ 55 table 20. smii timing parameters .............................................................................................. ........................................ 56 table 21. auto-negotiation fast link pulse (flp) timing parameters ............................................................ ................... 57 table 22. mdc/mdio timing parameters .......................................................................................... ................................. 58 table 23. reset timing parameters ............................................................................................. ....................................... 59 table 24. transformer selection criteria ...................................................................................... ....................................... 62 table 25. qualified single port magnetics..................................................................................... ...................................... 62 table 26. typical referenc e crystal characteristics ........................................................................... ................................ 62
micrel, inc. ksz8041tl/ftl/mll december 2009 8 m9999-120909-1.2 pin configuration ? ksz8041tl 1 nc nc txc rst# intrp rext gnd rxer / rx_er / iso gnd vdd_1.8 gnd gnd gnd gnd xo vdda_3.3 nc txd1 / txd[1] / sync txd0 / txd[0] / tx txen / tx_en led1 / speed led0 / nwayen crs / config1 nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rx+ tx- rx- 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc vddio_3.3 vddio_3.3 rxdv / crsdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / rxd[1] / phyad2 rxd0 / rxd[0] / rx duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi / refclk / clock 15 tx+ 12 vdda_1.8 vdda_1.8 4 5 v1.8_out vdda_3.3 6 7 ksz8041tl 48-pin tqfp
micrel, inc. ksz8041tl/ftl/mll december 2009 9 m9999-120909-1.2 pin configuration ? ksz8041ftl 1 nc nc txc rst# intrp rext gnd rxer / rx_er / iso gnd vdd_1.8 gnd gnd gnd gnd xo vdda_3.3 fxsd / fxen txd1 / txd[1] / sync txd0 / txd[0] / tx txen / tx_en led1 / speed / no fef led0 / nwayen crs / config1 nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rx+ tx- rx- 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc vddio_3.3 vddio_3.3 rxdv / crsdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / rxd[1] / phyad2 rxd0 / rxd[0] / rx duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi / refclk / clock 15 tx+ 12 vdda_1.8 vdda_1.8 4 5 v1.8_out vdda_3.3 6 7 ksz8041ftl 48-pin tqfp
micrel, inc. ksz8041tl/ftl/mll december 2009 10 m9999-120909-1.2 pin description- ksz8041tl/ftl pin number pin name type (1) pin function 1 gnd gnd ground 2 gnd gnd ground 3 gnd gnd ground 4 vdda_1.8 p 1.8v analog v dd 5 vdda_1.8 p 1.8v analog v dd 6 v1.8_out p 1.8v output voltage from chip 7 vdda_3.3 p 3.3v analog v dd 8 vdda_3.3 p 3.3v analog v dd 9 rx- i/o physical receive or transmit signal (- differential) 10 rx+ i/o physical receive or transmit signal (+ differential) 11 tx- i/o physical transmit or receive signal (- differential) 12 tx+ i/o physical transmit or receive signal (+ differential) 13 gnd gnd ground 14 xo o crystal feedback this pin is used only in mii mode when a 25mhz crystal is used. this pin is a no connect if oscillator or ex ternal clock source is used, or if rmii mode or smii mode is selected. 15 xi / refclk / clock i crystal / oscillator / external clock input mii mode: 25mhz +/-50ppm (crystal, oscillator, or external clock) rmii mode: 50mhz +/-50ppm (oscillator, or external clock only) smii mode: 125mhz +/-100ppm (oscillator, or external clock only) 16 rext i/o set physical transmit output current connect a 6.49k resistor in parallel with a 100pf capacitor to ground on this pin. see ksz8041tl-ftl reference schematics. 17 gnd gnd ground 18 mdio i/o management interface (mii) data i/o this pin requires an external 4.7k pull-up resistor. 19 mdc i management interface (mii) clock input this pin is synchronous to the mdio data interface. 20 rxd3 / phyad0 ipu/o mii mode: receive data output[3] (2) / config. mode: the pull-up/pull-down value is latched as phyaddr[0] during power-up / reset. see strapping options section for details. 21 rxd2 / phyad1 ipd/o mii mode: receive data output[2] (2) / config. mode: the pull-up/pull-down value is latched as phyaddr[1] during power-up / reset. see strapping options section for details. 22 rxd1 / rxd[1] / phyad2 ipd/o mii mode: receive data output[1] (2) / rmii mode: receive data output[1] (3) / config. mode: the pull-up/pull-down value is latched as phyaddr[2] during power-up / reset. see strapping options section for details.
micrel, inc. ksz8041tl/ftl/mll december 2009 11 m9999-120909-1.2 pin number pin name type (1) pin function 23 rxd0 / rxd[0] / rx duplex ipu/o mii mode: receive data output[0] (2) / rmii mode: receive data output[0] (3) / smii mode: receive data and control (4) / config. mode: latched as duplex (register 0h, bit 8) during power-up / reset. see strapping options section for details. 24 gnd gnd ground 25 vddio_3.3 p 3.3v digital v dd 26 vddio_3.3 p 3.3v digital v dd 27 rxdv / crsdv / config2 ipd/o mii mode: receive data valid output / rmii mode: carrier sense/receive data valid output / config. mode: the pull-up/pull-down value is latched as config2 during power-up / reset. see strapping options section for details. 28 rxc o mii mode: receive clock output. 29 rxer / rx_er / iso ipd/o mii mode: receive error output / rmii mode: receive error output / config. mode: the pull-up/pull-down value is latched as isolate during power-up / reset. see strapping options section for details. 30 gnd gnd ground 31 vdd_1.8 p 1.8v digital v dd 32 intrp opu interrupt output: programmable interrupt output register 1bh is the interrupt control/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 9 sets the interrupt output to active low (default) or active high. 33 txc i/o mii mode: transmit clock output mii back-to back mode: transmit clock input 34 txen / tx_en i mii mode: transmit enable input / rmii mode: transmit enable input 35 txd0 / txd[0] / tx i mii mode: transmit data input[0] (5) / rmii mode: transmit data input[0] (6) / smii mode: transmit data and control (7) 36 txd1 / txd[1] / sync i mii mode: transmit data input[1] (5) / rmii mode: transmit data input[1] (6) / smii mode: sync clock input 37 gnd gnd ground 38 txd2 i mii mode: transmit data input[2] (5) / 39 txd3 i mii mode: transmit data input[3] (5) / 40 col / config0 ipd/o mii mode: collision detect output / config. mode: the pull-up/pull-down value is latched as config0 during power-up / reset. see strapping options section for details. 41 crs / config1 ipd/o mii mode: carrier sense output / config. mode: the pull-up/pull-down value is latched as config1 during power-up / reset. see strapping options section for details.
micrel, inc. ksz8041tl/ftl/mll december 2009 12 m9999-120909-1.2 pin number pin name type (1) pin function 42 (ksz8041tl) led0 / nwayen ipu/o led output: programmable led0 output / config. mode: latched as auto-negotiati on enable (register 0h, bit 12) during power-up / reset. see strapping options section for details. the led0 pin is programmable via register 1eh bits [15:14], and is defined as follows. led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] reserved led mode = [11] reserved 42 (ksz8041ftl) led0 / nwayen ipu/o led output: programmable led0 output / config. mode: if copper mode (fxen= 0), latched as auto-negotiation enable (register 0h, bit 12) during power-up / reset. if fiber mode (fxen=1), this pin configuration is always strapped to disable auto-negotiation. see strapping options section for details. the led0 pin is programmable via register 1eh bits [15:14], and is defined as follows. led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] reserved led mode = [11] reserved
micrel, inc. ksz8041tl/ftl/mll december 2009 13 m9999-120909-1.2 pin number pin name type (1) pin function 43 (ksz8041tl) led1 / speed ipu/o led output: programmable led1 output / config. mode: latched as speed (register 0h, bit 13) during power-up / reset. see strapping options section for details. the led1 pin is programmable via register 1eh bits [15:14], and is defined as follows. led mode = [00] speed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10] reserved led mode = [11] reserved 43 (ksz8041ftl) led1 / speed / no fef ipu/o led output: programmable led1 output / config. mode: if copper mode (fxen=0), latched as speed (register 0h, bit 13) during power-up / reset. if fiber mode (fxen=1), latched as no fef (no far-end fault) during power-up / reset. see strapping options section for details. the led1 pin is programmable via register 1eh bits [15:14], and is defined as follows. led mode = [00] speed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10] reserved led mode = [11] reserved 44 nc - no connect 45 nc - no connect 46 nc - no connect
micrel, inc. ksz8041tl/ftl/mll december 2009 14 m9999-120909-1.2 pin number pin name type (1) pin function 47 rst# i chip reset (active low) 48 (ksz8041tl) nc - no connect 48 (ksz8041ftl) fxsd / fxen ipd fxsd: signal detect for 100base-fx fiber mode fxen: fiber enable for 100base-fx fiber mode if fxen=0, fiber mode is disabled. phy is in copper mode. the default is 0. see 100base-fx operation section for details. notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipd = input with internal pull-down (40k +/-30%). ipu = input with internal pull-up (40k +/-30%). opu = output with internal pull-up (40k +/-30%). ipu/o = input with internal pull-up (40k +/-30%) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (40k +/-30%) during power-up/reset; output pin otherwise. 2. mii rx mode: the rxd[3..0] bits are synchronous with rxclk. when rxdv is asserted, rxd[3..0] presents valid data to mac th rough the mii. rxd[3..0] is invalid when rxdv is de-asserted. 3. rmii rx mode: the rxd[1:0] bits are synchronous with ref_clk. for each clock period in which crs_dv is asserted, two bits of recovered data are sent from the phy. 4. smii rx mode: receive data and control information are sent in 10 bit segments. in 100mbit mode, each segment represents a new byte of data. in 10mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. the mac can sample any one of every 10 segments in 10mbit mode. 5. mii tx mode: the txd[3..0] bits are synchronous with txclk. when txen is asserted, txd[3..0] presents valid data from the mac through the mii. txd[3..0] has no effect when txen is de-asserted. 6. rmii tx mode: the txd[1:0] bits are synchronous with ref_clk. for each clock period in which tx_en is asserted, two bits o f data are received by the phy from the mac. 7. smii tx mode: transmit data and control information are received in 10 bit segments. in 100mbit mode, each segment represe nts a new byte of data. in 10mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. the phy can sample any one of every 10 segments in 10mbit mode.
micrel, inc. ksz8041tl/ftl/mll december 2009 15 m9999-120909-1.2 strapping options- ksz8041tl/ftl pin number pin name type (1) pin function 22 21 20 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at power-up / reset and is configurable to any value from 1 to 7. the default phy address is 00001. phy address bits [4:3] are always set to 00. 27 41 40 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap-in pins are latched at power-up / reset and are defined as follows: config[2:0] mode 000 mii (default) 001 rmii 010 smii 011 reserved C not used 100 mii 100mbps preamble restore 101 rmii back-to-back 110 mii back-to-back 111 reserved C not used 29 iso ipd/o isolate mode pull-up = enable pull-down (default) = disable during power-up / reset, this pin value is latched into register 0h bit 10. 43 (ksz8041tl) speed ipu/o speed mode pull-up (default) = 100mbps pull-down = 10mbps during power-up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. speed / if copper mode (fxen=0), pin strap-in is speed mode. pull-up (default) = 100mbps pull-down = 10mbps during power-up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. 43 (ksz8041ftl) no fef ipu/o if fiber mode (fxen=1), pin strap-in is no fef. pull-up (default) = enable far-end fault pull-down = disable far-end fault this pin value is latched during power-up / reset.
micrel, inc. ksz8041tl/ftl/mll december 2009 16 m9999-120909-1.2 pin number pin name type (1) pin function 23 duplex ipu/o duplex mode pull-up (default) = half duplex pull-down = full duplex during power-up / reset, this pin value is latched into register 0h bit 8 as the duplex mode. 42 (ksz8041tl) nwayen ipu/o nway auto-negotiation enable pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation during power-up / reset, this pin value is latched into register 0h bit 12. if copper mode (fxen=0), pin strap-in is nway auto-negotiation enable. pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation during power-up / reset, this pin value is latched into register 0h bit 12. 42 (ksz8041ftl) nwayen ipu/o if fiber mode (fxen=1), this pin configuration is always strapped to disable auto- negotiation. note: 1. ipu/o = input with internal pull-up (40k +/-30%) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (40k +/-30%) during power-up/reset; output pin otherwise. pin strap-ins are latched during power-up or reset. in some systems, the mac receive input pins may drive high during power-up or reset, and consequently cause the phy strap-in pins on the mii/rmii/smii signals to be latched high. in this case, it is recommended to add 1k pull-downs on these phy strap-in pins to ensure the phy does not strap-in to isolate mode, or is not configured with an incorrect phy address.
micrel, inc. ksz8041tl/ftl/mll december 2009 17 m9999-120909-1.2 pin configuration ?KSZ8041MLL 1 nc nc txc rst# intrp rext gnd rxer / iso gnd vdd_1.8 gnd gnd gnd gnd xo vdda_3.3 nc txd1 txd0 txen led1 / speed led0 / nwayen crs / config1 nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rx+ tx- rx- 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc vddio_3.3 vddio_3.3 rxdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / phyad2 rxd0 / duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi 15 tx+ 12 vdda_1.8 vdda_1.8 4 5 v1.8_out vdda_3.3 6 7 KSZ8041MLL 48-pin lqfp
micrel, inc. ksz8041tl/ftl/mll december 2009 18 m9999-120909-1.2 pin description? KSZ8041MLL pin number pin name type (1) pin function 1 gnd gnd ground 2 gnd gnd ground 3 gnd gnd ground 4 vdda_1.8 p 1.8v analog v dd 5 vdda_1.8 p 1.8v analog v dd 6 v1.8_out p 1.8v output voltage from chip 7 vdda_3.3 p 3.3v analog v dd 8 vdda_3.3 p 3.3v analog v dd 9 rx- i/o physical receive or transmit signal (- differential) 10 rx+ i/o physical receive or transmit signal (+ differential) 11 tx- i/o physical transmit or receive signal (- differential) 12 tx+ i/o physical transmit or receive signal (+ differential) 13 gnd gnd ground 14 xo o crystal feedback this pin is used only when a 25 mhz crystal is used. this pin is a no connect if oscillator or external clock source is used. 15 xi i crystal / oscillator / external clock input 25mhz +/-50ppm 16 rext i/o set physical transmit output current connect a 6.49k resistor in parallel with a 100pf capacitor to ground on this pin. see KSZ8041MLL reference schematic. 17 gnd gnd ground 18 mdio i/o management interface (mii) data i/o this pin requires an external 4.7kpull-up resistor. 19 mdc i management interface (mii) clock input this pin is synchronous to the mdio data interface. 20 rxd3 / phyad0 ipu/o mii mode: receive data output[3] (2) / config. mode: the pull-up/pull-down value is latched as phyaddr[0] during power-up / reset. see strapping options section for details. 21 rxd2 / phyad1 ipd/o mii mode: receive data output[2] (2) / config. mode: the pull-up/pull-down value is latched as phyaddr[1] during power-up / reset. see strapping options section for details. 22 rxd1 / phyad2 ipd/o mii mode: receive data output[1] (2) / config. mode: the pull-up/pull-down value is latched as phyaddr[2] during power-up / reset. see strapping options section for details. 23 rxd0 / duplex ipu/o mii mode: receive data output[0] (2) / config mode: latched as duplex (register 0h, bit 8) during power-up / reset. see strapping options section for details. 24 gnd gnd ground 25 vddio_3.3 p 3.3v digital v dd 26 vddio_3.3 p 3.3v digital v dd
micrel, inc. ksz8041tl/ftl/mll december 2009 19 m9999-120909-1.2 pin number pin name type (1) pin function 27 rxdv / config2 ipd/o mii mode: receive data valid output / config. mode: the pull-up/pull-down value is latched as config2 during power-up / reset. see strapping options section for details. 28 rxc o mii receive clock output 29 rxer / iso ipd/o mii mode: receive error output / config. mode: the pull-up/pull-down value is latched as isolate during power-up / reset. see strapping options section for details. 30 gnd gnd ground 31 vdd_1.8 p 1.8v digital v dd 32 intrp opu interrupt output: programmable interrupt output register 1bh is the interrupt control/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 9 sets the interrupt output to active low (default) or active high. 33 txc i/o mii transmit clock output 34 txen i mii transmit enable input 35 txd0 i mii transmit data input[0] (3) 36 txd1 i mii transmit data input[1] (3) 37 gnd gnd ground 38 txd2 i mii transmit data input[2] (3) / 39 txd3 i mii transmit data input[3] (3) / 40 col / config0 ipd/o mii mode: collision detect output / config. mode: the pull-up/pull-down value is latched as config0 during power-up / reset. see strapping options section for details. 41 crs / config1 ipd/o mii mode: carrier sense output / config. mode: the pull-up/pull-down value is latched as config1 during power-up / reset. see strapping options section for details. 42 led0 / nwayen ipu/o led output: programmable led0 output / config. mode: latched as auto-negotiati on enable (register 0h, bit 12) during power-up / reset. see strapping options section for details. the led0 pin is programmable via register 1eh bits [15:14], and is defined as follows. led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] reserved led mode = [11] reserved
micrel, inc. ksz8041tl/ftl/mll december 2009 20 m9999-120909-1.2 pin number pin name type (1) pin function 43 led1 / speed ipu/o led output: programmable led1 output / config. mode: latched as speed (register 0h, bit 13) during power-up / reset. see strapping options section for details. the led1 pin is programmable via register 1eh bits [15:14], and is defined as follows. led mode = [00] speed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10] reserved led mode = [11] reserved 44 nc - no connect 45 nc - no connect 46 nc - no connect 47 rst# i chip reset (active low) 48 nc - no connect notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipd = input with internal pull-down (40k +/-30%). ipu = input with internal pull-up (40k +/-30%). opu = output with internal pull-up (40k +/-30%). ipu/o = input with internal pull-up (40k +/-30%) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (40k +/-30%) during power-up/reset; output pin otherwise. 2. mii rx mode: the rxd[3..0] bits are synchronous with rxclk. when rxdv is asserted, rxd[3..0] presents valid data to mac th rough the mii. rxd[3..0] is invalid when rxdv is de-asserted. 3. mii tx mode: the txd[3..0] bits are synchronous with txclk. when txen is asserted, txd[3..0] presents valid data from the mac through the mii. txd[3..0] has no effect when txen is de-asserted.
micrel, inc. ksz8041tl/ftl/mll december 2009 21 m9999-120909-1.2 strapping options ? KSZ8041MLL pin number pin name type (1) pin function 22 21 20 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at power-up / reset and is configurable to any value from 1 to 7. the default phy address is 00001. phy address bits [4:3] are always set to 00. 27 41 40 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap-in pins are latched at power-up / reset and are defined as follows: config[2:0] mode 000 mii (default) 001 reserved C not used 010 reserved C not used 011 reserved C not used 100 mii 100mbps preamble restore 101 reserved C not used 110 mii back-to-back 111 reserved C not used 29 iso ipd/o isolate mode pull-up = enable pull-down (default) = disable during power-up / reset, this pin value is latched into register 0h bit 10. 43 speed ipu/o speed mode pull-up (default) = 100mbps pull-down = 10mbps during power-up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. 23 duplex ipu/o duplex mode pull-up (default) = half duplex pull-down = full duplex during power-up / reset, this pin value is latched into register 0h bit 8 as the duplex mode. 42 nwayen ipu/o nway auto-negotiation enable pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation during power-up / reset, this pin value is latched into register 0h bit 12. note: 1. ipu/o = input with internal pull-up (40k +/-30%) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (40k +/-30%) during power-up/reset; output pin otherwise. pin strap-ins are latched during power-up or reset. in some systems, the mac receive input pins may drive high during power-up or reset, and consequently ca use the phy strap-in pins on the mii signals to be latched high. in this case, it is recommended to add 1k pull-downs on these phy strap-in pins to ensure the phy does not strap-in to isolate mode, or is not configured with an incorrect phy address.
micrel, inc. ksz8041tl/ftl/mll december 2009 22 m9999-120909-1.2 functional description the ksz8041tl is a single 3.3v supply fast ethernet transceiver. it is fully compliant with the ieee 802.3u specification. on the media side, the ksz8041tl supports 10base-t and 100base-tx with hp auto mdi/mdi-x for reliable detection of and correction for straight-through and crossover cables. the ksz8041tl offers a choice of mii, rmii, or smii data interface connection to a mac processor. the mii management bus option gives the mac processor complete access to the ksz8041tl control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status change. physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. the ksz8041ftl has all the identical rich features of the ksz8041tl plus 100base-fx fiber support. the KSZ8041MLL is the basic 10base-t/100base-tx copper version with mii support. 100base-tx transmit the 100base-tx transmit function performs para llel-to-serial conversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 6.49 k 1% resistor for the 1:1 transformer ratio. it has typical rise/fall times of 4 ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot and timing jitter. the wave- shaped 10base-t output drivers are also incorporated into the 100base-tx drivers. 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based upon comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. pll clock synthesizer the ksz8041tl/ftl/mll generates 125mhz, 25mhz and 20mhz clocks for system timing. in mii mode, internal clocks are generated from an external 25mhz crystal or oscillator. for the ksz8041tl/ftl, in rmii and smii modes, these internal clocks are generated from external 50mhz and 125mhz oscillators or system clocks, respectively. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. 10base-t transmit the 10base-t drivers are incorporated with the 100base-tx drivers to allow for transmission using the same magnetic. the drivers also perform internal wave-shaping and pre-emphasize, and output 10base-t signals with a typical amplitude of 2.5v peak. the 10base-t signals have harmonic contents that are at least 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal.
micrel, inc. ksz8041tl/ftl/mll december 2009 23 m9999-120909-1.2 10base-t receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a pll performs the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths to prevent noise at the rx+ and rx- inputs from falsely trigger the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8041tl/ftl/mll decodes a data frame. the receive clock is kept active during idle periods in between data reception. sqe and jabber function (10base-t only) in 10base-t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is required as a test of the 10base-t transmit/receive path. if transmit enable (txen) is high for more than 20ms (jabbering), the 10base-t transmitter is disabled and col is asserted high. if txen is then driven low for more than 250ms, the 10base- t transmitter is re-enabled and col is de-asserted (returns to low). auto-negotiation the ksz8041tl/ftl/mll conforms to the auto-negotiation protocol, defined in clause 28 of the ieee 802.3u specification. auto-negotiation is enabled by either hardware pin strapping (pin 42) or software (register 0h bit 12). auto-negotiation allows unshielded twisted pair (utp) link partners to select the highest common mode of operation. link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. priority 1: 100base-tx, full-duplex priority 2: 100base-tx, half-duplex priority 3: 10base-t, full-duplex priority 4: 10base-t, half-duplex if auto-negotiation is not supported or the ksz8041tl/ftl/mll link partne r is forced to bypass auto-negotiation, the ksz8041tl/ftl/mll sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the ksz8041tl/ftl/mll to establish link by listening for a fixed signal protocol in the absence of auto- negotiation advertisement protocol. the auto-negotiation link up process is shown in the following flow chart.
micrel, inc. ksz8041tl/ftl/mll december 2009 24 m9999-120909-1.2 start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles a ttempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow n o yes yes no figure 1. auto-negotiation flow chart
micrel, inc. ksz8041tl/ftl/mll december 2009 25 m9999-120909-1.2 mii management (miim) interface the ksz8041tl/ftl/mll supports the ieee 802.3 mii management interface, also known as the management data input / output (mdio) interface. this interface allows uppe r-layer devices to monitor a nd control the state of the ksz8041tl/ftl/mll. an external device with miim capability is used to read the phy status and/or configure the phy settings. further details on the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: a physical connection that incorporates the clock line (mdc) and the data line (mdio). a specific protocol that operates across the aforementioned physical connection that allows a external controller to communicate with one or more phy devices. each ksz8041tl/ftl/mll device is assigned a unique phy address between 1 and 7 by its phyad[2:0] strapping pins. also, every ksz8041tl/ftl/mll device supports the broadcast phy address 0, as defined per the ieee 802.3 specification, which can be used to read/write to a single ksz8041tl/ftl/mll device, or write to multiple ksz8041tl/ftl/mll devices simultaneously. a set of 16-bit mdio registers. register [0:6] are required, and their functions are defined per the ieee 802.3 specification. the additional registers are provided for expanded functionality. the following table shows the mii management frame format for the ksz8041tl/ftl/mll. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z table 1. mii ma nagement frame format interrupt (intrp) intrp (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the ksz8041tl/ftl/mll phy register. bits[15:8] of register 1bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the intrp signal. bits[7:0] of register 1bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading register 1bh. bit 9 of register 1fh sets the interrupt level to active high or active low. mii data interface the media independent interface (mii) is specified in clause 22 of the ieee 802.3 specification. it provides a common interface between physical layer and mac layer devices, and has the following key characteristics: supports 10mbps and 100mbps data rates. uses a 25mhz reference clock, sourced by the phy. provides independent 4-bit wide (nibble) transmit and receive data paths. contains two distinct groups of signals: one for transmission and the other for reception. by default, the ksz8041tl/ftl/mll is configured to mii mode after it is power-up or reset with the following: a 25mhz crystal connected to xi, xo (pins 15, 14), or an external 25mhz clock source (oscillator) connected to xi. configuration[2:0] (pins 27, 41, 40) set to 000 (default setting).
micrel, inc. ksz8041tl/ftl/mll december 2009 26 m9999-120909-1.2 mii signal definition the following table describes the mii signals. refer to claus e 22 of the ieee 802.3 specification for detailed information. mii signal name direction (with respect to phy, ksz8041tl/ftl/mll signal) direction (with respect to mac) description txc output input transmit clock (2.5 mhz for 10mbps; 25 mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data [3:0] rxc output input receive clock (2.5 mhz for 10mbps; 25 mhz for 100mbps) rxdv output input receive data valid rxd[3:0] output input receive data [3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection table 2. mii signal definition transmit clock (txc) txc is sourced by the phy. it is a continuous clock that provides the timing reference for txen and txd[3:0]. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. transmit enable (txen) txen indicates the mac is presenting nibbles on txd[3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the mii, and is negated prior to the first txc following the final nibble of a frame. txen transitions synchronously with respect to txc. transmit data [3:0] (txd[3:0]) txd[3:0] transitions synchronously with respect to txc. when txen is asserted, txd[3:0] are accepted for transmission by the phy. txd[3:0] is 00 to indicate idle when txen is de-asserted. values other than 00 on txd[3:0] while txen is de-asserted are ignored by the phy. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[3:0], and rxer. in 10mbps mode, rxc is recovered from the line while carrier is active. rxc is derived from the phys reference clock when the line is idle, or link is down. in 100mbps mode, rxc is continuously recovered from the line. if link is down, rxc is derived from the phys reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation.
micrel, inc. ksz8041tl/ftl/mll december 2009 27 m9999-120909-1.2 receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on rxd[3:0]. in 10mbps mode, rxdv is asserted with the first nibble of the sfd (start of frame delimiter), 5d, and remains asserted until the end of the frame. in 100mbps mode, rxdv is asserted from the first nibble of the preamble to the last nibble of the frame. rxdv transitions synchronously with respect to rxc. receive data [3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. receive error (rxer) rxer is asserted for one or more rxc periods to indicate that a symbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetectable by the mac sub-layer) was detected somewhere in the frame presently being transferred from the phy. rxer transitions synchronously with respect to rxc. while rxdv is de-asserted, rxer has no effect on the mac. carrier sense (crs) crs is asserted and de-asserted as follows: in 10mbps mode, crs assertion is based on the reception of valid preambles. crs de-assertion is based on the reception of an end-of-frame (eof) marker. in 100mbps mode, crs is asserted when a start-of-stream delimiter, or /j/k symbol pair is detected. crs is de- asserted when an end-of-stream delimiter, or /t/r symbol pair is detected. additionally, the pma layer de-asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. this is used to inform the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. reduced mii (rmii) data interface (ksz8041tl/ftl only) the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). it provides a common interface between physical layer and mac layer devices, and has the following key characteristics: supports 10mbps and 100mbps data rates. uses a single 50mhz reference clock provided by the mac or the system board. provides independent 2-bit wide (di-bit) transmit and receive data paths. contains two distinct groups of signals: one for transmission and the other for reception. the ksz8041tl/ftl is configured in rmii mode after it is power-up or reset with the following: a 50 mhz reference clock connected to refclk (pin 15). config[2:0] (pins 27, 41, 40) set to 001. in rmii mode, unused mii signals, txd[3:2] (pins 39, 38), are tied to ground.
micrel, inc. ksz8041tl/ftl/mll december 2009 28 m9999-120909-1.2 rmii signal definition (ksz8041tl/ftl only) the following table describes the rmii signals. refer to rmii specification for detailed information. rmii signal name direction (with respect to phy, ksz8041tl/ftl signal) direction (with respect to mac) description ref_clk input input, or output synchronous 50 mhz clock reference for receive, transmit and control interface tx_en input output transmit enable txd[1:0] input output transmit data [1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data [1:0] rx_er output input, or (not required) receive error table 3. rmii signal description reference clock (ref_clk) ref_clk is sourced by the mac or system board. it is a continuous 50 mhz clock that provides the timing reference for tx_en, txd[1:0], crs_dv, rxd[1:0], and rx_er. transmit enable (tx_en) tx_en indicates that the mac is presenting di-bits on txd[1:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the rmii, and is negated prior to the first ref_clk following the final di-bit of a frame. tx_en transitions synchronously with respect to ref_clk. transmit data [1:0] (txd[1:0]) txd[1:0] transitions synchronously with respect to ref_clk. when tx_en is asserted, txd[1:0] are accepted for transmission by the phy. txd[1:0] is 00 to indicate idle when tx_en is de-asserted. values ot her than 00 on txd[1:0] while tx_en is de-asserted are ignored by the phy. carrier sense/receive data valid (crs_dv) crs_dv is asserted by the phy when the receive medium is non-idle. it is asserted asynchronously on detection of carrier. this is when squelch is passed in 10mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in 100mbps mode. loss of carrier results in the de-assertion of crs_dv. so long as carrier detection criteria are met, crs_dv remains asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit, and it is negated prior to the first ref_clk that follows the final di-bit. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] is "00" until proper receive signal decoding takes place. receive data [1:0] (rxd[1:0]) rxd[1:0] transitions synchr onously to ref_clk. for each clock period in which crs_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. rxd[1:0] is "00" to indi cate idle when crs_dv is de-a sserted. values other than 00 on rxd[1:0] while crs_dv is de-asserted are ignored by the mac. receive error (rx_er) rx_er is asserted for one or more ref_clk periods to indicate that a symbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetectable by the mac sub-layer) was detected somewhere in the frame presently being transferred from the phy. rx_er transitions synchronously with respect to ref_clk. while crs_dv is de-asserted, rx_er has no effect on the mac.
micrel, inc. ksz8041tl/ftl/mll december 2009 29 m9999-120909-1.2 collision detection the mac regenerates the col signal of the mii from tx_en and crs_dv. serial mii (smii) data interface (ksz8041tl/ftl only) the serial media independent interface (smii) is the lowest pin count media independent interface (mii). it provides a common interface between physical layer and mac layer devices, and has the following key characteristics: supports 10mbps and 100mbps data rates. uses 125mhz reference clock provided by the mac or the system board. uses 12.5mhz sync pulse provided by the mac. provides independent single-bit wide transmit and receive data paths for data and control information. the ksz8041tl/ftl is configured in smii mode after it is power-up or reset with the following: a 125mhz reference clock connected to clock (pin 15). a 12.5mhz sync pulse connected to sync (pin 36). configuration[2:0] (pins 27, 41, 40) set to 010. in smii mode, unused mii signals, txd[3:2] (pins 39, 38), are tied to ground. smii signal definition (ksz8041tl/ftl only) the following table describes the smii signals. refer to smii specification for detailed information. smii signal name direction (with respect to phy, ksz8041tl/ftl signal) direction (with respect to mac) description clock input input, or output 125 mhz clock reference for receive and transmit data and control sync input output 12.5 mhz sync pulse from mac tx input output transmit data and control rx output input receive data and control table 4. smii signal description clock reference (clock) clock is sourced by the mac or system board. it is a continuous 125 mhz clock that provides the timing reference for sync, tx, and rx. sync pulse (sync) sync is a 12.5mhz synchronized pulse derived from clock by the mac. it is used to indicate the segment boundary for each transmit data/control segment, or receive data/control segment. each segment is comprised of ten bits. sync is generated continuously by the mac at every ten cycles of clock. transmit data and control (tx) tx provides transmit data and control information from mac-to-phy in 10-bit segments. in 10mbps mode, each segment is repeated ten times. therefore, every ten segments represent a new byte of data. the phy can sample any one of every ten segments. in 100mbps mode, each segment represents a new byte of data.
micrel, inc. ksz8041tl/ftl/mll december 2009 30 m9999-120909-1.2 the following figure and table shows the transmit data/control format for each segment: tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 clock sync tx figure 2. smii transmit data/control segment smii tx bit description tx_er transmit error tx_en transmit enable txd[0:7] encoded data see smii txd[0:7] encoding table (below) table 5. smii tx bit description tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 x 0 use to force an error in a direct mac-to- mac connection speed 0=10m 1=100m duplex 0=half 1=full link 0=down 1=up jabber 0=no 1=yes 1 1 1 x 1 one data byte table 6. smii txd[0 :7] encoding table receive data and control (rx) rx provides receive data and control information from phy-to-mac in 10-bit segments. in 10mbps mode, each segment is repeated ten times. therefore, every ten segments represent a new byte of data. the mac can sample any one of every ten segments. in 100mbps mode, each segment represents a new byte of data.
micrel, inc. ksz8041tl/ftl/mll december 2009 31 m9999-120909-1.2 the following figure and table shows the receive data/control format for each segment: crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 clock sync rx figure 3. smii receive data/control segment smii rx bit description crs carrier sense rx_dv receive data valid rxd[0:7] encoded data see smii rxd[0:7] encoding table (below) table 7. smii rx bit description crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 x 0 rx_er from pervious frame speed 0=10m 1=100m duplex 0=half 1=full link 0=down 1=up jabber 0=no 1=yes upper nibble 0=invalid 1=valid false carrier detected 1 x 1 one data byte table 8. smii rxd[0:7] encoding table collision detection collisions occur when crs and tx_en are simultaneously asserted. the mac regenerates the mii collision signal from crs and tx_en.
micrel, inc. ksz8041tl/ftl/mll december 2009 32 m9999-120909-1.2 hp auto mdi/mdi-x hp auto mdi/mdi-x configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the ksz8041tl/ftl/mll and its link partner. this feature allows the ksz8041tl/ftl/mll to use either type of cable to connect with a link partner that is in either mdi or mdi-x mode. the auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the ksz8041tl/ftl/mll accordingly. hp auto mdi/mdi-x is enabled by default. it is disabled by writing a one to register 1f bit 13. mdi and mdi-x mode is selected by register 1f bit 14 if hp auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and receive data paths is recommended to support auto mdi/mdi-x. the ieee 802.3 standard defines mdi and mdi-x as follow: mdi mdi-x rj-45 pin signal rj-45 pin signal 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 9. mdi/mdi-x pin definition straight cable a straight cable connects a mdi device to a mdi-x device, or a mdi-x device to a mdi device. the following diagram depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi-x). receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) figure 4. typical straight cable connection
micrel, inc. ksz8041tl/ftl/mll december 2009 33 m9999-120909-1.2 crossover cable a crossover cable connects a mdi device to another mdi device, or a md i-x device to another mdi-x device. the following diagram depicts a typical crossover cable connection between two switches or hubs (two mdi-x devices). receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) crossover cable figure 5. typical crossover cable connection
micrel, inc. ksz8041tl/ftl/mll december 2009 34 m9999-120909-1.2 linkmd ? cable diagnostics the linkmd ? feature utilizes time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits and impedance mismatches. linkmd ? works by sending a pulse of known amplitude and duration down the mdi and mdi-x pairs, and then analyzing the shape of the reflected signal. timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of +/-2m. internal circuitry computes the tdr information and presents it in a user-readable digital format. note: cable diagnostics are only valid for copper connections and do not support fiber optic operation. access linkmd ? is initiated by accessing register 1dh, the linkmd ? control/status register, in conjunction with register 1fh, the phy control 2 register. usage the following test procedure demonstrates how to use linkmd ? for cable diagnostic: 1. disable auto mdi/mdi-x by writing a 1 to register 1fh bit 13 to enable manual control over the differential pair used to transmit the linkmd ? pulse. 2. select the differential pair to transmit the linkmd ? pulse with register 1fh bit 14. 3. start cable diagnostic test by writing a 1 to register 1dh bit 15. this enable bit is self-clearing. 4. wait (poll) for register 1dh bit 15 to return a 0, indicating cable diagnostic test is completed. 5. read cable diagnostic test results in register 1dh bits [14:13]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the 11 case, invalid test, occurs if the ksz8041tl/ftl/mll is unable to shut down the link partner. in this instance, the test is not run, since it would be impossible for the ksz8041tl/ftl/mll to determine if the detected signal is a reflection of the signal generated by the ksz8041tl/ftl/mll, or a signal from its link partner. 6. get distance to fault by multiplying the decimal value in register 1dh bits [8:0] by a constant of 0.4. the distance, d (expressed in meters), to the cable fault is determined by the following formula: d (distance to cable fault) = 0.4 x {decimal value of register 1dh bits [8:0]} the 0.4 constant can be calibrated for different cable types and cabling conditions, such as cables with velocity of propagation that varies significantly from the norm. power management the ksz8041tl/ftl/mll offers the following power management modes: power saving mode this mode is used to reduce power consumption when the cable is unplugged. it is in effect when auto-negotiation mode is enabled, cable is disconnected, and register 1fh bit 10 is set to 1. under power saving mode, the ksz8041tl/ftl/mll shuts down all transceiver blocks, except for transmitter, energy detect and pll circuits. additionally, in mii mode, the rxc clock output is disabled. rxc clock is enabled after the cable is connected and link is established. power saving mode is disabled by writing a zero to register 1fh bit 10. power down mode this mode is used to power down the entire ksz8041tl/ftl/mll device when it is not in use. power down mode is enabled by writing a one to register 0h bit 11. in the power down state, the ksz8041tl/ftl/mll disables all internal functions, except for the mii management interface.
micrel, inc. ksz8041tl/ftl/mll december 2009 35 m9999-120909-1.2 reference clock connection options a crystal or clock source, such as an oscillator, is used to provide the reference clock for the ksz8041tl/ftl/mll. the following figure illustrates how to connect the 25mhz crystal and oscillator reference clock for mii mode. 25mhz osc +/-50ppm nc nc xi xo xi xo 22pf 22pf 22pf 22pf 25mhz xtal +/-50ppm figure 6. 25mhz crystal / oscillator reference clock for mii mode for the ksz8041tl/ftl, the following figure illustrates how to connect the 50mhz oscillator reference clock for rmii mode. figure 7. 50mhz oscillator reference clock for rmii mode for the ksz8041tl/ftl, the following figure illustrates how to connect the 125mhz oscillator reference clock for smii mode. 125mhz osc +/-100ppm nc nc clock xo figure 8. 125mhz oscillator reference clock for smii mode
micrel, inc. ksz8041tl/ftl/mll december 2009 36 m9999-120909-1.2 reference circuit for power and ground connections the ksz8041tl/ftl/mll is a single 3.3v supply device with a built-in 1.8v low noise regulator. the power and ground connections are shown in the following figure and table. figure 9. ksz8041tl/ftl/mll power and ground connections power pin pin number pin type description v1.8_out 6 output 1.8v supply output from ksz8041tl/ftl/mll decouple with 22uf and 0.1uf capacitors to ground. vdd_1.8 31 input connect to v1.8_out (pin 6) thru ferrite bead. decouple with 0.1uf capacitor to ground. vdda_1.8 4, 5 input connect to v1.8_out (pin 6) thru ferrite bead. decouple with 0.1uf capacitor on each pin to ground. vddio_3.3 25, 26 input connect to boards 3.3v supply. decouple with 22uf and 0.1uf capacitors to ground. vdda_3.3 7, 8 input connect to boards 3.3v supply thru ferrite bead. decouple with 22uf and 0.1uf capacitors to ground. table 10. ksz8041tl/ftl/mll power pin description
micrel, inc. ksz8041tl/ftl/mll december 2009 37 m9999-120909-1.2 100base-fx fiber operation (ksz8041ftl only) 100base-fx fiber operation is similar to 100base-tx copper operation with the differences being that the scrambler/de- scrambler and mlt3 encoder/decoder are bypassed on transmission and reception. in addition, auto-negotiation is bypassed, auto mdi/mdi-x is disabled, and speed is set to 100mbps. the duplex can be set to either half or full. usually, it is set to full-duplex. fiber signal detect in 100base-fx operation, fxsd (fiber signal detect), input pin 48, is usually connected to the fiber transceiver sd (signal detect) output pin. 100base-fx mode is activated when the fxsd input pin is greater than 1v. when fxsd is between 1v and 1.8v, no fiber signal is detected and a far-end fault is generated. when fxsd is over 2.2v, the fiber signal is detected. 100base-fx mode and signal detection is summarized in the following table: fxsd input voltage mode less than 0.2v copper mode greater than 1v, but less than 1.8v fiber mode no signal detected far-end fault generated (if enabled) greater than 2.2v fiber mode signal detected table 11. copper a nd fiber mode selection to ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver sd (signal detect) output voltage swing to match the fxsd pins input voltage threshold. alternatively, the far-end fault feature can be disabled. in this case, the fxsd input pin is tied high to 3.3v to force 100base-fx mode. far-end fault a far-end fault (fef) occurs when the signal detection is logically false on the receive side of the fiber transceiver. the ksz8041ftl detects a fef when its fxsd input (pin 48) is between 1v and 1.8v. when a fef is detected, the ksz8041ftl signals its fiber link partner that a fef has occurred by transmitting a repetitive pattern of 84-ones and 1- zero. this pattern is used to inform the fiber link partner that there is a faulty link on its transmit side. by default, fef is enabled. fef is disabled by strapping no fef (pin 43) low. see strapping options section for detail.
micrel, inc. ksz8041tl/ftl/mll december 2009 38 m9999-120909-1.2 back-to-back media converter a ksz8041tl/mll and a ksz8041ftl can be connected back-to-back to provide a low cost media converter solution. in back-to-back mode, media conversion is between 100base-tx copper and 100base-fx fiber. on the copper side, link up at 10base-t is not allowed, and is blocked during auto-negotiation. figure 10. ksz8041tl/mll and ksz8041ftl back-to-back media converter mii back-to-back mode in mii back-to-back mode, the ksz8041tl/mll interfaces with another ksz8041tl/mll, or a ksz8041ftl to provide a complete 100mbps repeater or media converter solution. the ksz8041tl/ftl/mll devices are configured to mii back-to- back mode after they are power-up or reset with the following: configuration[2:0] (pins 27, 41, 40) set to 110 a common 25mhz reference clock connected to xi (pin 15) mii signals connected as shown in the following table. KSZ8041MLL (100base-tx copper) ksz8041tl (100base-tx copper) KSZ8041MLL (100base-tx copper) ksz8041tl (100base-tx copper) ksz8041ftl (100base-fx fiber) pin name pin number pin type pin name pin number pin type rxc 28 output txc 33 input rxdv 27 output txen 34 input rxd3 20 output txd3 39 input rxd2 21 output txd2 38 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txc 33 input rxc 28 output txen 34 input rxdv 27 output txd3 39 input rxd3 20 output txd2 38 input rxd2 21 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output table 12. mii signal conne ction for mii back-to-back mode
micrel, inc. ksz8041tl/ftl/mll december 2009 39 m9999-120909-1.2 rmii back-to-back mode (ksz8041tl/ftl only) in rmii back-to-back mode, the ksz8041tl interfaces with another ksz8041tl, or a ksz8041ftl to provide a complete 100mbps repeater or media converter solution. the ksz8041tl/ftl devices are configured to rmii back-to-back mode after they are power-up or reset with the following: configuration[2:0] (pins 27, 41, 40) set to 101 a common 50mhz reference clock connected to refclk (pin 15) rmii signals connected as shown in the following table. ksz8041tl (100base-tx copper) ksz8041tl (100base-tx copper) ksz8041ftl (100base-fx fiber) pin name pin number pin type pin name pin number pin type crsdv 27 output txen 34 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txen 34 input crsdv 27 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output table 13. rmii signal connection for rmii back-to-back mode rmii back-to-back mode provides an option to disable the fiber side when the copper side is down. this, effectively, produces a link fault propagation for media converter applications, such that a copper side link down will automatically disable the fiber side. this ksz8041tl/ftl feature functions as follows: on the ksz8041tl copper side, rxd2 (pin 21) indicates if there is energy detected at the receive inputs of the copper port. rxd2 outputs a low if there is no energy detected (cable disconnected), and outputs a high if there is energy detected (cable connected). the rxd2 output of the ksz8041tl copper side drives the input of an inverter, and the output of the inverter drives the txd2 (pin 38) input of the ksz8041ftl fiber side. the fiber side transmitter is disabled if the txd2 input is high. the txd3 and txd2 pins should be pulled down with 1k resistors, and rxd3 and rxd2 pins should be left floating, if they are not used.
micrel, inc. ksz8041tl/ftl/mll december 2009 40 m9999-120909-1.2 register map register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h link partner next page ability 9h C 13h reserved 14h mii control 15h rxer counter 16h C 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd ? control/status 1eh phy control 1 1fh phy control 2 register description address name description mode (1) default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self-cleared after a 1 is written to it. rw/sc 0 0.14 loop-back 1 = loop-back mode 0 = normal operation rw 0 0.13 speed select (lsb) 1 = 100mbps 0 = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw set by speed strapping pin. see strapping options section for details. 0.12 auto- negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. rw set by nwayen strapping pin. see strapping options section for details. 0.11 power down 1 = power down mode 0 = normal operation rw 0 0.10 isolate 1 = electrical isolation of phy from mii and tx+/tx- 0 = normal operation rw set by iso strapping pin. see strapping options section for details. 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a 1 is written to it. rw/sc 0
micrel, inc. ksz8041tl/ftl/mll december 2009 41 m9999-120909-1.2 address name description mode (1) default 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw inverse of duplex strapping pin value. see strapping options section for details. 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:1 reserved ro 000_000 0.0 disable transmitter 0 = enable transmitter 1 = disable transmitter rw 0 register 1h ? basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full duplex 1 = capable of 100mbps full-duplex 0 = not capable of 100mbps full-duplex ro 1 1.13 100base-tx half duplex 1 = capable of 100mbps half-duplex 0 = not capable of 100mbps half-duplex ro 1 1.12 10base-t full duplex 1 = capable of 10mbps full-duplex 0 = not capable of 10mbps full-duplex ro 1 1.11 10base-t half duplex 1 = capable of 10mbps half-duplex 0 = not capable of 10mbps half-duplex ro 1 1.10:7 reserved ro 0000 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = capable to perform auto-negotiation 0 = not capable to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). kendin communications oui is 0010a1 (hex) ro 0022h
micrel, inc. ksz8041tl/ftl/mll december 2009 42 m9999-120909-1.2 address name description mode (1) default register 3h ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24 th bits of the organizationally unique identifier (oui). kendin communications oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manufacturers model number ro 01_0001 3.3:0 revision number four bit manufacturers revision number ro indicate silicon revision register 4h ? auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability rw set by speed strapping pin. see strapping options section for details. 4.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability rw set by speed strapping pin. see strapping options section for details. 4.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h ? auto-negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause ro 00
micrel, inc. ksz8041tl/ftl/mll december 2009 43 m9999-120909-1.2 address name description mode (1) default 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0001 register 6h ? au to-negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection. ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7h ? auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow 0 = last page rw 0 7.14 reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? link partner next page ability 8.15 next page 1 = additional next page(s) will follow 0 = last page ro 0
micrel, inc. ksz8041tl/ftl/mll december 2009 44 m9999-120909-1.2 address name description mode (1) default 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 14h ? mii control 14.15:8 reserved ro 0000_0000 14.7 100base-tx preamble restore 1 = restore received preamble to mii output (random latency) 0 = consume 1-byte preamble before sending frame to mii output for fixed latency rw 0 or 1 (if config[2:0] = 100) see strapping options section for details. 14.6 10base-t preamble restore 1 = restore received preamble to mii output 0 = remove all 7-bytes of preamble before sending frame (starting with sfd) to mii output rw 0 14.5:0 reserved ro 00_0001 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h register 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link down interrupt enable 1 = enable link down interrupt 0 = disable link down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0
micrel, inc. ksz8041tl/ftl/mll december 2009 45 m9999-120909-1.2 address name description mode (1) default 1b.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occurred ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occurred ro/sc 0 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occurred ro/sc 0 1b.2 link down interrupt 1 = link down occurred 0 = link down did not occurred ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occurred ro/sc 0 1b.0 link up interrupt 1 = link up occurred 0 = link up did not occurred ro/sc 0 register 1dh ? linkmd ? control/status 1d.15 cable diagnostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12:9 reserved 0000 1d.8:0 cable fault counter distance to fault; its approximately 0.4m*(cable fault counter value in decimal) ro 0_0000_0000 register 1eh ? phy control 1 1e.15:14 led mode [00] = led1 : speed led0 : link/activity [01] = led1 : activity led0 : link [10], [11] = reserved rw 00 1e.13 polarity 0 = polarity is not reversed 1 = polarity is reversed ro
micrel, inc. ksz8041tl/ftl/mll december 2009 46 m9999-120909-1.2 address name description mode (1) default 1e.12 far-end fault detect 0 = far-end fault not detected 1 = far-end fault detected this bit applies to ksz8041ftl fiber only. ro 0 1e.11 mdi/mdi-x state 0 = mdi 1 = mdi-x ro 1e.10:8 reserved 1e.7 remote loopback 0 = normal mode 1 = remote (analog) loop back is enable rw 0 1e.6:0 reserved register 1fh ? phy control 2 1f.15 hp_mdix 0 = micrel auto mdi/mdi-x mode 1 = hp auto mdi/mdi-x mode rw 1 1f.14 mdi/mdi-x select when auto mdi/mdi-x is disabled, 0 = mdi mode transmit on tx+/- (pins 12,11) and receive on rx+/- (pins 10,9) 1 = mdi-x mode transmit on rx+/- (pins 10,9) and receive on tx+/- (pins 12,11) rw 0 1f.13 pairswap disable 1 = disable auto mdi/mdi-x 0 = enable auto mdi/mdi-x rw 0 1f.12 energy detect 1 = presence of signal on rx+/- analog wire pair 0 = no signal detected on rx+/- ro 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allow transmitter to send pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving if power saving mode is enabled and the cable is disconnected, the rxc clock output (in mii mode) is disabled. rxc clock is enabled after the cable is connected and link is established. rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1f.6 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0
micrel, inc. ksz8041tl/ftl/mll december 2009 47 m9999-120909-1.2 address name description mode (1) default 1f.5 phy isolate 1 = phy in isolate mode 0 = phy in normal operation ro 0 1f.4:2 operation mode indication [000] = still in auto-negotiation [001] = 10base-t half-duplex [010] = 100base-tx half-duplex [011] = reserved [101] = 10base-t full-duplex [110] = 100base-tx full-duplex [111] = reserved ro 000 1f.1 enable sqe test 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 note: 1. rw = read/write. ro = read only. sc = self-cleared. lh = latch high. ll = latch low.
micrel, inc. ksz8041tl/ftl/mll december 2009 48 m9999-120909-1.2 absolute maximum ratings (1) supply voltage (v dd_1.8, v dda_1.8, v 1.8_out ) ........................ -0.5v to +2.4v (v ddio_3.3, v dda_3.3 ) ................................... -0.5v to +4.0v input voltage (all inputs) ............................... -0.5v to +4.0v output voltage (all outputs) .......................... -0.5v to +4.0v lead temperature (solderi ng, 10sec.)....................... 260c storage temperature (t s ) ..........................-55c to +150c operating ratings (2) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v ambient temperature (t a , commercial) ........ 0c to +70c ambient temperature (t a , industrial)..........-40c to +85c maximum junction temperature (t j max) ................. 125c thermal resistance ( ja ) ....................................69.64c/w thermal resistance ( jc ) .........................................15c/w electrical characteristics (3) symbol parameter condition min typ max units supply current (4) i dd1 100base-tx chip only (no transformer); full-duplex traffic @ 100% utilization 53.0 58.3 ma i dd2 10base-t chip only (no transformer); full-duplex traffic @ 100% utilization 38.0 41.8 ma i dd3 power saving mode ethernet cable disconnected (reg. 1f.10 = 1) 32.0 35.2 ma i dd4 power down mode software power down (reg. 0.11 = 1) 4.0 4.4 ma ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = gnd ~ v ddio -10 10 a ttl outputs v oh output high voltage i oh = -4ma 2.4 v v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri-state leakage 10 a led outputs i led output drive current each led pin (led0, led1) 8 ma 100base-tx transmit (measured di fferentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % v set reference voltage of i set 0.65 v output jitter peak-to-peak 0.7 1.4 ns 10base-t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak-to-peak 3.5 ns t r , t f rise/fall time 25 ns 10base-t receive v sq squelch threshold 5mhz square wave 400 mv
micrel, inc. ksz8041tl/ftl/mll december 2009 49 m9999-120909-1.2 notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause pe rmanent damage to the device. operation of the device at these or any other conditions above those specified in the operating section s of this specification is not implied. maximum conditions for extended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25 c. specification for packaged product only. 4. current consumption is for the single 3.3v supply ksz8041tl/ftl/mll device only, and includes the 1.8v supply voltage (v dd_1.8, v dda_1.8, v 1.8_out ) that is provided by the ksz8041tl/ftl/mll. the phy ports transformer consumes an additional 45ma @ 3.3v for 100base-tx and 70 ma @ 3.3v for 10base-t.
micrel, inc. ksz8041tl/ftl/mll december 2009 50 m9999-120909-1.2 timing diagrams mii sqe timing (10base-t) txc t sqe col t sqep txen t wl t wh t p figure 11. mii sqe timing (10base-t) timing parameter description min typ max unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de-asserted 2.5 s t sqep col (sqe) pulse duration 1.0 s table 14. mii sqe timing (10base-t) parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 51 m9999-120909-1.2 mii transmit timing (10base-t) txc t hd2 t su2 txen txd[3:0] t su1 t hd1 crs t crs2 t crs1 t wh t wl t p figure 12. mii transmit timing (10base-t) timing parameter description min typ max unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 160 ns t crs2 txen low to crs de-asserted latency 510 ns table 15. mii transmit timing (10base-t) parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 52 m9999-120909-1.2 mii receive timing (10base-t) figure 13. mii receive timing (10base-t) timing parameter description min typ max unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rxc pulse width high 200 ns t od (rxd[3:0], rxer, rxdv) output delay from rising edge of rxc 182 225 ns t rlat crs to (rxd[3:0], rxer, rxdv) latency 6.5 s table 16. mii receive timing (10base-t) parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 53 m9999-120909-1.2 mii transmit timing (100base-tx) figure 14. mii transmit timing (100base-tx) timing parameter description min typ max unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 34 ns t crs2 txen low to crs de-asserted latency 33 ns table 17. mii transmit timing (100base-tx) parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 54 m9999-120909-1.2 mii receive timing (100base-tx) figure 15. mii receive timing (100base-tx) timing parameter description min typ max unit t p rxc period 40 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxd[3:0], rxer, rxdv) output delay from rising edge of rxc 19 25 ns crs to rxdv latency 140 ns crs to rxd[3:0] latency 52 ns t rlat crs to rxer latency 60 ns table 18. mii receive timing (100base-tx) parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 55 m9999-120909-1.2 rmii timing refclk tcyc tx_en txd[1:0] t1 t2 transmit timing figure 16. rmii timing ? data received from rmii refclk tcyc tod crsdv rxd[1:0] receive timing figure 17. rmii timing ? data input to rmii timing parameter description min typ max unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 3 9 ns table 19. rmii timing parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 56 m9999-120909-1.2 smii timing figure 18. smii timing ? data received from smii figure 19. smii timing ? data input to smii timing parameter description min typ max unit t su setup time 1.5 ns t hd hold time 1.0 ns t od output delay 4.0 5.0 ns table 20. smii timing parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 57 m9999-120909-1.2 auto-negotiation timing auto-negotiation fast link pulse (flp) timing t pw tx+/tx- clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx+/tx- data pulse flp burst flp burst figure 20. auto-negotiation fast link pulse (flp) timing timing parameter description min typ max units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 table 21. auto-negotiation fast link pulse (flp) timing parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 58 m9999-120909-1.2 mdc/mdio timing t md1 valid data mdio (phy input) valid data mdc t md2 mdio (phy output) valid data t md3 t p figure 21. mdc/mdio timing timing parameter description min typ max unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 222 ns table 22. mdc/mdio timing parameters
micrel, inc. ksz8041tl/ftl/mll december 2009 59 m9999-120909-1.2 reset timing the ksz8041tl/ftl/mll reset timing requirement is summarized in the following figure and table. tsr tcs tch trc supply voltage rst# strap-in value strap-in / output pin figure 22. reset timing parameter description min max units t sr stable supply voltage to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap-in pin output 6 ns table 23. reset timing parameters after the de-assertion of reset, it is recommended to wait a minimum of 100s before starting programming on the miim (mdc/mdio) interface.
micrel, inc. ksz8041tl/ftl/mll december 2009 60 m9999-120909-1.2 reset circuit the following reset circuit is recommended for powering up the ksz8041tl/ftl/mll if reset is triggered by the power supply. ksz8041tl/ftl/mll 3.3v d1 d1: 1n4148 r 10k c 10uf rst# figure 23. recommended reset circuit the following reset circuit is recommended for applications where reset is driven by another device (e.g., cpu or fpga). at power-on-reset, r, c and d1 provide the necessary ramp rise time to reset the ksz8041tl/ftl/mll device. the rst_out_n from cpu/fpga provides the warm reset after power up. figure 24. recommended reset circuit for interfacing with cpu/fpga reset output ksz8041tl/ftl/mll cpu/fpga 3.3v c 10uf r 10k rst_out_n d1 d2 d1, d2: 1n4148 rst#
micrel, inc. ksz8041tl/ftl/mll december 2009 61 m9999-120909-1.2 the following figure shows the reference circuits for pull-up, float and pull-down on the led1 and led0 strapping pins. led pin 3.3v pull-up ksz8041tl/ftl/mll 3.3v float ksz8041tl/ftl/mll led pin 3.3v pull-down ksz8041tl/ftl/mll led pin figure 25. reference circuits for led strapping pins
micrel, inc. ksz8041tl/ftl/mll december 2009 62 m9999-120909-1.2 selection of isolation transformer a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode chokes is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350h 100mv, 100khz, 8ma leakage inductance (max.) 0.4h 1mhz (min.) inter-winding capacitance (typ.) 12pf d.c. resistance (typ.) 0.9 insertion loss (max.) -1.0db 0mhz C 65mhz hipot (min.) 1500vrms table 24. transformer selection criteria magnetic manufacturer part number auto mdi-x number of port bel fuse s558-5999-u7 yes 1 bel fuse (mag jack) si-46001 yes 1 bel fuse (mag jack) si-50170 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 tdk (mag jack) tla-6t718 yes 1 table 25. qualified single port magnetics selection of reference crystal characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm load capacitance 20 pf series resistance 40 table 26. typical reference crystal characteristics
micrel, inc. ksz8041tl/ftl/mll december 2009 63 m9999-120909-1.2 package information 48-pin lqfp 48-pin (7mm x 7mm) lqfp package
micrel, inc. ksz8041tl/ftl/mll december 2009 64 m9999-120909-1.2 48-pin tqfp , s n o i s u r t o r p r o h s a l f d l o m e d u l c n i t o n s e o d n o i s n e m i d . m m 4 5 2 . 0 d e e c x e t o n l l a h s h c i h w f o r e h t i e . n o i s u r t o r p r a b m a d e d u l c n i t o n s e o d n o i s n e m i d d a e l m o t t o b n a h t r e l l a m s e r a s n o i s n e m i d d l o m p o t e g a k c a p g n a h r e v o t o n l l i w e g a k c a p f o p o t d n a s n o i s n e m i d d l o m . e g a k c a p f o m o t t o b : s e t o n . 1 . 2 . 3 . 4 48-pin (7mm x 7mm) tqfp package note: all dimensions are in millimeters.
micrel, inc. ksz8041tl/ftl/mll december 2009 65 m9999-120909-1.2 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a si gnificant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2008 micrel, incor p orated.

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